1. Field of the Invention
The present invention relates to semiconductor circuits, and more particularly, to a circuit for replacing defective cells with redundant cells in a semiconductor memory device.
2. Description of the Prior Art
Recently, in a large scale semiconductor memory device, in order to increase the reduced production yield caused by defects in memory cells generated during the manufacturing process which often render the entire chip useless, redundancy schemes are widely used.
Redundancy is to provide an on-chip spare memory array in addition to a normal memory array, and, when one or more memory cells in the normal memory array are faulty, to replace rows or columns containing the defective normal memory cell or cells with rows or columns containing the defect-free redundant cell or cells.
Currently, the substitution of good cells for defective cells in normal memory arrays is implemented by electrically or physically disconnecting faulty rows or columns of cells from the normal memory array and electrically connecting redundant rows or columns to the row or column address decoder in such a manner that each responds to the address bit pattern which formerly selected the faulty row or column. Such redundancy is performed either before or after packaging of the memory chip and has been accomplished by using one of two methods, i.e., one of blowing polysilicon fuses by use of pulses of electrical current, and the other of vaporization of conductor material with accurately focused laser beam spots.
However, as memory arrays become more dense and line widths grow smaller, the laser redundancy technology has the problem of requirement for highly expensive apparatus accurately controlling the magnitude and the position of the laser beam spots. Meanwhile, the electrically polysilicon fuse-blowing redundancy has another problem of arranging as well additional circuits on the same chip for supplying so large currents as to cut open polysilicon fuses as pheripheral circuits while protecting those circuit elements from destruction by large fuse blowing current. This creates the drawback of an enevitable increase in chip size or area.
In addition to the above mentioned redundancy schemes, there has been another one which is to substitute redundant rows or columns for defective rows or columns by programming nonvolatile memory elements so as to be selectively enabled the corresponding redundant row or column whenever the row or column having defective normal memory cells is addressed.
Various circuits for performing such substitution are set forth in U.S. Pat. Nos. 4,422,161 to Kressel et al. and 4,514,830 to Hagiwara et al. However, these patents need to employ a plurality of nonvolatile memory elements for the replacement of faulty cells.
However, the greatest problem of the redundancy scheme which arises from using such nonvolatile memory elements is the reliability of the element itself. If any one of the nonvolatile memory elements programmed in order to be substituted for rows or columns containing defective cells is faulty, information stored in the memory elements will be lost and the replacement of bad cells will not be performed.